A power semiconductor device is a semiconductor device which has a high withstand voltage and is used in applications in which a large current is conducted therethrough, and it is required to have a low loss. Recently, a power semiconductor device is used in a high-speed inverter. There is also a demand for high-speed operations in such applications.
Power semiconductor devices were conventionally produced using silicon (Si) substrates. In recent years, however, power semiconductor devices using silicon carbide (SiC) have drawn attention and have been developed (see, for example, Patent Document Nos. 1-4).
The breakdown voltage of the silicon carbide material itself is greater than that of silicon by one order of magnitude. Therefore, when a power semiconductor device is produced using silicon carbide, the reverse breakdown voltage can be maintained even if the depletion layer at the pn junction or the Schottky barrier junction is made thinner. Therefore, by decreasing the thickness of the device and increasing the doping concentration of the silicon carbide layer, it is possible to realize a power semiconductor device having a low ON resistance, a high withstand voltage and a low loss. Also, the saturation electron velocity of silicon carbide is about twice that of silicon, and it is possible to realize a high-speed operation.
Patent Document No. 1 discloses a silicon carbide semiconductor device with increased channel mobility and decreased ON resistance. FIG. 37 is a cross-sectional view illustrating the silicon carbide semiconductor device disclosed in Patent Document No. 1.
A silicon carbide semiconductor device 1000 shown in FIG. 37 is a vertical-type metal insulator semiconductor field effect transistor (hereinafter a “MISFET”), and has a planar structure. The semiconductor device 1000 includes a semiconductor substrate 101 containing n+-type SiC. A first silicon carbide layer 120 of silicon carbide is provided on the principal surface of the semiconductor substrate 101. A p-type body region 104 having a predetermined depth is formed in a predetermined region of a surface portion of the first silicon carbide layer 120. A portion of the first silicon carbide layer 120 other than the body region 104 serves as an n−-type drift region 102. An n+-type first impurity region (source region) 103 is formed in the vicinity of the surface of the body region 104. A contact region 207 is provided in the body region 104. A second silicon carbide layer 105 connecting the first impurity region 103 and the drift region 102 with each other is arranged so as to cover the surface portion of the body region 104. A gate electrode 108 is formed on the surface of the second silicon carbide layer 105 with a gate oxide film 107 interposed therebetween.
An interlayer insulating film 109 is provided on the surface of the first silicon carbide layer 120 so as to cover the gate electrode 108. A contact hole is provided in the interlayer insulating film 109, through which the first impurity region 103 and the contact region 207 are exposed, and a first ohmic electrode (source electrode) 122 is provided in the contact hole, with an interconnect 110 further provided therein. A contact hole, through which the gate electrode 108 is exposed, is provided in the interlayer insulating film 109, and an interconnect 112 is provided in the contact hole. A metal silicide layer 123 is formed between the interconnect 112 and the gate electrode 108. A second ohmic electrode (drain electrode) 111 is formed on the reverse surface of the semiconductor substrate 101.
In the semiconductor device 1000 shown in FIG. 37, by applying a voltage between the first ohmic electrode 122 and the gate electrode 108 to give an electric field to the gate oxide film 107, an accumulation channel 41 is induced in the second silicon carbide layer 105, whereby carriers flow between the first ohmic electrode 122 and the second ohmic electrode 111.
By operating the semiconductor device 1000 in an accumulation mode for inducing a channel, it is possible to increase the channel mobility and reduce the ON resistance as compared with a case in which it is operated in an inversion mode where a channel is induced by inverting the conductivity type.
Next, referring to FIGS. 38 to 46, a method for manufacturing the silicon carbide semiconductor device 1000 will be described. First, as shown in FIG. 38, the semiconductor substrate 101 containing n+-type SiC is prepared, and the first silicon carbide layer 120 of n−-type SiC is formed on the principal surface thereof by an epitaxial growth method. Then, a first implantation mask 72 having openings formed therein in regions to be the body region 104 is formed.
The ion implantation for forming the body region 104 is performed while heating the semiconductor substrate 101 at a temperature of 400° C. to 600° C. An organic resist typically has poor heat resistance and is not suitable for the first implantation mask 72. Therefore, an inorganic film such as a silicon oxide film, a polysilicon or a silicon nitride film is formed on the principal surface of the first silicon carbide layer 120, with an organic resist mask formed thereon, and the inorganic film is etched using the organic resist mask to remove the organic resist. Thus, the heat-resistant first implantation mask 72 is obtained. FIG. 38 shows a cross section after the organic resist is removed and the body region 104 is formed. Hereinafter, masks for ion implantation are formed by a similar method. A portion of the first silicon carbide layer 120 other than the body region 104 serves as the drift region 102.
As shown in FIG. 39, after an inorganic film is deposited on the surface of the first silicon carbide layer 120 so as to cover the first implantation mask 72, an organic resist mask, which has a pattern that defines regions to be contact regions, is formed on the inorganic film (not shown). The inorganic film is anisotropically etched by a dry etching method using the organic resist mask, thereby forming a first sidewall 71 located on the side wall of the first implantation mask 72, and a second implantation mask 78 covering the contact region. An impurity is ion-implanted into the body region 104 using the first sidewall 71 and the second implantation mask 78, thereby forming the first impurity region 103.
Next, as shown in FIG. 40, after the first implantation mask 72, the first sidewall 71 and the second implantation mask 78 are removed, a third implantation mask 73 having openings formed therein in regions to be contact regions is formed on the surface of the first silicon carbide layer 120, and an aluminum ion, for example, is implanted into the first silicon carbide layer 120, thereby forming the contact region 207.
As shown in FIG. 41, after the third implantation mask 73 is removed, annealing is performed at a temperature of 1000° C. or more, e.g., 1700° C., thereby activating the impurities which have been implanted (not shown). Then, the second silicon carbide layer 105 is deposited on the principal surface of the first silicon carbide layer 120. As shown in FIG. 42, a photoresist 76, which defines the second silicon carbide layer 105, is formed, and unnecessary portions of the second silicon carbide layer 105 are removed by dry etching.
As shown in FIG. 43, the gate oxide film 107 is formed on the second silicon carbide layer 105, and the gate electrode 108 is formed thereon. Moreover, as shown in FIG. 44, the interlayer insulating film 109 is formed across the entire surface of the first silicon carbide layer 120 so as to cover the gate electrode 108. As shown in FIG. 45, a contact hole 109a, through which the gate electrode 108 is exposed, and a contact hole 109b, through which the contact region 207 and the first impurity region 103 are exposed, are formed in the interlayer insulating film 109.
As shown in FIG. 46, the first ohmic electrode 122 and the interconnect 110 are formed in the contact hole 109b, and the metal silicide layer 123 and the interconnect 112 are formed in the contact hole 109a. The second ohmic electrode 111 is formed on the reverse surface of the semiconductor substrate 101. Thus, the semiconductor device 1000 is completed.